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1m x 32 static ram elm road, west chirton industrial estate, north shields, ne29 8se, england. tel +44 (0191) 2930500. fax +44 (0191) 2590997 description signal address input a0~a18 data input/output d0~d31 chip select /cs1~4 write enable /we output enable /oe no connect nc power v cc ground v ss pin functions block diagram pin definition see page 2. package details puma 68 - plastic 68 ?j leaded package max. dimensions (mm) - 25.27 x 25.27 x 5.08 features ? access times of 15, 20 and 25ns. ? 3.3v + 10%. ? commercial, industrial and military temperature grade. ? jedec standard 68 j lead footprint. ? industry standard pinout. ? may be organised as 1m x 32, 2m x 16 ? completely static operation. puma 68sv32000 - 015/020/25 issue 2.1 july 2002 description the puma68 range of devices provide a high density surface mount industry standard memory solution which may accommodate various memory technologies including sram, eeprom and flash. the devices are designed to offer a defined upgrade path and may be user configured as 16 or 32 bits wide. the puma68sv32000 is a 1mx32 sram module housed in a 68 jleaded package which complies with the jedec 68 plcc standard. access times of 20 or 25ns are available. the 3.3v low voltage device is available to commercial, industrial and military temperature grade. the part is constructed using 8x512kx8 sram bga, with four fitted to the top of the module and four to the bottom. 512k x 8 sram 512k x 8 sram 512k x 8 sram 512k x 8 sram 512k x 8 sram 512k x 8 sram 512k x 8 sram 512k x 8 sram d0~7 d8~15 d16~23 d24~31 d0~7 d8~15 d16~23 d24~31 cs1 cs2 cs4 cs3 a0~18 /oe /we
issue 2.1 july 2002 page 2 pin definition - puma68sv32000 pin signal pin signal 1 gnd 35 /oe 2 /cs3 36 /cs2 3 a5 37 a17 4 a4 38 nc 5 a3 39 nc 6 a2 40 nc 7 a1 41 a18 8 a0 42 gnd 9 nc 43 nc 10 d0 44 d31 11 d1 45 d30 12 d2 46 d29 13 d3 47 d28 14 d4 48 d27 15 d5 49 d26 16 d6 50 d25 17 d7 51 d24 18 gnd 52 gnd 19 d8 53 d23 20 d9 54 d22 21 d10 55 d21 22 d11 56 d20 23 d12 57 d19 24 d13 58 d18 25 d14 59 d17 26 d15 60 d16 27 vcc 61 vcc 28 a11 62 a10 29 a12 63 a9 30 a13 64 a8 31 a14 65 a7 32 a15 66 a6 33 a16 67 /we 34 /cs1 68 /cs4
timing waveforms page 3 issue 2.1 july 2002 parameter symbol min typ max unit supply voltage v cc 3.0 3.3 3.6 v input high voltage v ih 2.0 - v cc +0.3 v input low voltage v il (1) -0.3 - 0.8 v operating temperature t a 0 - 70 o c t ai -40 - 85 o c (i suffix) t am -55 - 125 o c (m suffix) absolute maximum ratings (1) recommended operating conditions dc electrical characteristics (v cc =3.3v +10%, t a =-55 o c to +125 o c) parameter symbol min max unit voltage on any pin relative to v ss v t -0.3 to +4.6 v power dissipation p t 4.2 w storage temperature t stg -55 to +125 o c notes : (1) stresses above those listed may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability notes (1) /cs1~2 or /cs3~4 inputs operate simultaneously for 32 bit mode and singly for 16 bit mode. (2) at f=f max address and data inputs are cycling at max frequency. parameter symbol test condition min typ max unit input leakage current i li v in =0v to v cc -16 - 16 a output leakage current i lo v i/o =0v to v cc -16 - 16 a operating supply current (2) 32 bit i cc32 /cs (1) =v il , i i/o =0ma,f=f max - - 880 ma 16 bit i cc16 as above. - - 680 ma standby supply current ttl i sb /cs (1) =v ih ,min cycle - - 480 ma output voltage low v ol i ol =8.0ma - - 0.4 v output voltage high v oh i oh =-4.0ma 2.4 - - v
timing waveforms page 4 issue 2.1 july 2002 166? 30pf i/o pin 1.76v capacitance (v cc = 5.0v, t a = 25 o c, f=1mhz.) parameter symbol test condition min typ max unit input capacitance, address, /oe, /we c in1 v in =0v - - 58 pf output capacitance, 8 bit mode (worst case) c i/o v i/o =0v - - 66 pf test conditions output load ? input pulse levels : 0v to 3.0v ? input rise and fall times : 3ns ? input and output timing reference levels : 1.5v ? output load : see load diagram. ?v cc = 3.3v +10% ? puma module tested in 32 bit mode. note : these parameters are calculated not measured. /cs1 /cs2 /cs3 /cs4 /oe /we supply current mode l h h h x l i cc16 write d0~d15 h l h h x l i cc16 write d16~d31 h h l h x l i cc16 write d0~d15 h h h l x l i cc16 write d16~d31 l l h h x l i cc32 write d0~d31 h h l l x l i cc32 write d0~d31 l h h h l h i cc16 read d0~d15 h l h h l h i cc16 read d16~d31 h h l h l h i cc16 read d0~d15 h h h l l h i cc16 read d16~d31 l l h h l h i cc32 read d0~d31 h h l l l h i cc32 read d0~d31 x x x x h h i cc32 /i cc16 d0~d31 high-z h h h h x x i sb d0~d31 standby operation truth table notes : h=v ih : l=vi l : x=v ih or v il
timing waveforms page 5 issue 2.1 july 2002 read cycle write cycle 15 20 25 parameter symbol min max min max min max units read cycle time t rc 15 - 20 - 25 - ns address access time t aa - 15 - 20 - 25 ns chip select access time t acs - 15 - 20 - 25 ns output enable to output valid t oe - 7 - 9 - 11 ns output hold from address change t oh 3 - 3 - 3 - ns chip selection to output in low z t clz 3 - 3 - 3 - ns output enable to output in low z t olz 0 - 0 - 0 - ns chip deselection to output in high z t chz 0 7 0 9 0 11 ns output disable to output in high z t ohz 0 7 0 9 0 11 ns 15 20 25 parameter symbol min max min max min max units write cycle time t wc 15 - 20 - 25 - ns chip selection to end of write t cw 12 - 14 - 16 - ns address valid to end of write t aw 12 - 14 - 16 - ns address setup time t as 0 - 0 - 0 - ns write pulse width (/oe high) t wp1 12 - 14 - 16 - ns write recovery time t wr 0 - 0 - 0 - ns write to output in high z t whz 0 7 0 9 0 11 ns data to write time overlap t dw 8 - 10 - 12 - ns data hold time from write time t dh 0 - 0 - 0 - ns output active from end of write t ow 3 - 3 - 3 - ns
timing waveforms page 6 issue 2.1 july 2002 address data out valid data t rc t aa t acs t olz t clz(4,5) t chz(3,4,5) t ohz t oh /cs /oe notes (read cycle) 1. /we is high for read cycle. 2. all read cycle timing is referenced from the last valid address to the first transition address. 3. t chz and t ohz are defined as the time at which the outputs achieve the open circuit condition and are not referenced to v oh or v ol levels. 4. at any given temperature and voltage condition, t chz (max.) is less than t clz (min.) both for a given device and from device to device. 5. transition is measured 200mv from steady state voltage with load(b). this parameter is sampled and not 100% tested. 6. device is continuously selected with /cs=v il . 7. address valid prior to coincident with /cs transition low. 8. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cyc le. 9. /cs=/cs1~4 t oe previous data valid data valid address data out t rc t aa t oh read cycle 1 (address controlled, /cs=/oe=v il , /we=v ih ) read cycle 2 (/we = v ih )
timing waveforms page 7 issue 2.1 july 2002 valid data address /oe /cs data in data out t wc t aw t wr(5) t cw(3) t as(4) t wp(2) t dw t dh t ohz(6) hi g h z hi g h z(8) /we notes (write cycle) 1. all write cycle timing is referenced from the last valid address to the first transition address. 2. a write occurs during the overlap of a low /cs and /we. a write begins at the latest transition /cs going low and /we going low ; a write ends at the earliest transition /cs going high or /we going high. t wp is measured from the beginning of write to the end of write. 3. t cw is measured from the later of /cs going low to end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. t wr applied in case a write ends as /cs or /we going high. 6. if oe, /cs and /we are in the read mode during this period, the i/o pins are in the output low-z state. inputs of opposite p hase of the output must not be applied because bus contention can occur. 7. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cyc le. 8. if /cs goes low simultaneously with /we going or after /we going low, the outputs remain high impedance state. 9. dout is the read data of the new address. 10. when /cs is low : i/o pins are in the output state. the input signals in the opposite phase leading to the output should not be applied. 11 ./cs=/cs1~4 write cycle 1 (/oe = clock)
timing waveforms page 8 issue 2.1 july 2002 write cycle 2 (/oe = low fixed) /cs address data in data out t wc t aw t wr(5) t cw(3) t as(4) t wp(2) t whz(6) hi g h z hi g h z(8) /we valid data t dw t dh t ow (10) (9) notes (write cycle) 1. all write cycle timing is referenced from the last valid address to the first transition address. 2. a write occurs during the overlap of a low /cs and /we. a write begins at the latest transition /cs going low and /we going low ; a write ends at the earliest transition /cs going high or /we going high. t wp is measured from the beginning of write to the end of write. 3. t cw is measured from the later of /cs going low to end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. t wr applied in case a write ends as /cs or /we going high. 6. if oe, /cs and /we are in the read mode during this period, the i/o pins are in the output low-z state. inputs of opposite p hase of the output must not be applied because bus contention can occur. 7. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cyc le. 8. if /cs goes low simultaneously with /we going or after /we going low, the outputs remain high impedance state. 9. dout is the read data of the new address. 10. when /cs is low : i/o pins are in the output state. the input signals in the opposite phase leading to the output should not be applied. 11 ./cs=/cs1~4
timing waveforms page 9 issue 2.1 july 2002 write cycle 3 (/cs = controlled) /cs address data in data out t wc t aw t wr(5) t cw(3) t as(4) t wp(2) t whz(6) hi g h z hi g h z(8) /we valid data t dw t dh t lz hi g h z hi g h z notes (write cycle) 1. all write cycle timing is referenced from the last valid address to the first transition address. 2. a write occurs during the overlap of a low /cs and /we. a write begins at the latest transition /cs going low and /we going low ; a write ends at the earliest transition /cs going high or /we going high. t wp is measured from the beginning of write to the end of write. 3. t cw is measured from the later of /cs going low to end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. t wr applied in case a write ends as /cs or /we going high. 6. if /oe, /cs and /we are in the read mode during this period, the i/o pins are in the output low-z state. inputs of opposite phase of the output must not be applied because bus contention can occur. 7. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cyc le. 8. if /cs goes low simultaneously with /we going or after /we going low, the outputs remain high impedance state. 9. dout is the read data of the new address. 10. when /cs is low : i/o pins are in the output state. the input signals in the opposite phase leading to the output should not be applied. 11 /cs=/cs1~4
timing waveforms page 10 issue 2.1 july 2002 puma 68 pin jedec surface mount plcc 25.02 (0.985) sq. 25.27 (0.995) sq. 1.27 typ. 0.46 typ. 0.10 (0.004) (0.210) max 5.33 24.13 (0.950) 23.11 (0.910) 0.90 (0.035) typ. (0.050) (0.018) pin 1 pin 68
ordering information page 11 issue 1.0 march 2001 ordering information note : although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for a particular purpose. our products are subject to a constant process of development. data may be changed without notice. products are not authorised for use as critical components in life support devices without the express written approval of a company director. puma68sv32000abi-020 access time 020 = 20ns 025 = 25ns temperature blank = commercial i = industrial m = military b = csp based features a = 4x / we version blank = 1x /we version organisation 32000 = 32mbit 1m x 32 or 2m x 16 technology sv = sram 3.3v vcc package puma68 = 68 jlead plcc 015 = 15ns
customer guidelines page 12 issue 1.0 february 2001 visual inspection standard all devices inspected to ansi/j-std-001b class 2 standard moisture sensitivity devices are moisture sensitive. shelf life in sealed bag 12 months at <40 o c and <90% relative humidity (rh). after this bag has been opened, devices that will be subjected to infrared reflow, vapour phase reflow, or equivalent processing (peak package body temp 220 o c) must be : a : mounted within 72 hours at factory conditions of <30 o c/60% rh or b : stored at <20% rh if these conditions are not met or indicator card is >20% when read at 23 o c +/-5% devices require baking as specified below. if baking is required, devices may be baked for :- a : 24 hours at 125 o c +/-5% for high temperature device containers or b : 192 hours at 40 o c +5 o c/-0 o c and <5% rh for low temperature device containers . packaging standard devices packaged in dry nitrogen, jed-std-020. packaged in trays as standard. tape and reel available for shipment quantities exceeding 200pcs upon request. soldering recomendations ir/convection - ramp rate 6 o c/sec max. temp. exceeding 183 o c 150 secs. max. peak temperature 225 o c time within 5 o c of peak 20 secs max. ramp down 6 o c/sec max. vapour phase - ramp up rate 6 o c/sec max. peak temperature 215 - 219 o c time within 5 o c of peak 60 secs max. ramp down 6 o c/sec max. the above conditions must not be exceeded note : the above recomendations are based on standard industry practice. failiure to comply with the above recomendations invalidates product warranty.

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